In order to optimize the performance of complex systems, it is of utmost importance to pay close attention to the handling of the data flow through these systems. Data paths are often pipelined to improve throughput. Back pressure flow control, using various forms of handshaking mechanisms which allow the data to stall in the pipeline if the forward path is congested, is sometimes used in these pipelines.
To implement full back pressure flow control, at least two handshake phases are required. This means that in synchronously clocked systems, either two registers are needed for each pipeline stage (an extra stall buffer is required to allow a clock cycle for reacting by stalling the data, if the pipeline is congested in the forward direction), or else only every other clock cycle can be used for transferring data. Alternatively, pipeline stages can be clocked on both rising and falling clock edges; however this requires complex dual edge triggered logic in the pipeline stages.
Systems of this type may be found in e.g., US 2005024110 to Klass and U.S. Pat. No. 4,980,851 to Komori et al.
A synchronous system is an abstraction, in that a physically implemented system will never be ideally synchronous. Variability in clock line delays causes unpredictable skew between clocking signals at different pipeline stages. This skew can result in circuit failure. Also, it is of great importance in complex system's to use as little power as possible, hence data routing circuits should only be clocked when there is data to be routed.